1. Field of Invention
One or more embodiments of the present invention relate to the electronic field. More specifically, embodiments relate to non-volatile memory devices.
2. Discussion of the Related Art
Non-volatile memory devices are used in any application that requires the storing of binary digits (or bits) of information that should be stored even when the memory devices are not powered.
An example of such memory devices is represented by E2PROM (Electrically Erasable and programmable read-only memory) memory devices. In general, each E2PROM memory device includes a matrix of memory cells, each one of which may be both programmed and erased electrically. Each memory cell includes two transistors: a memory transistor for storing the information bit and a selection transistor for selectively accessing the memory transistor during a reading, programming or erasing operation thereof. The memory transistor is typically a MOS transistor with a floating gate structure; such transistor has a drain terminal, a source terminal and a control terminal (control gate), in a totally similar manner to a standard MOS transistor, with the addition of a further floating control region (floating gate) that is buried in an oxide layer in order to be electrically isolated.
The information bit is physically stored, in the form of electric charge, within the floating gate; in fact a change of electric charge within the floating gate defines a corresponding change of a threshold voltage of the memory transistor; in particular, the memory cell is programmed at a low value of the threshold voltage (when electric charges are present within the floating gate) and erased at a high value of the threshold voltage (when the floating gate is free from electric charges). Such change of the threshold voltage determines, during a reading operation of the memory cell, a corresponding modulation of a channel current through the memory transistor, whose value represents the information bit stored in the memory cell.
Because of some criticalities detected in the memory cells during the programming operation thereof, the E2PROM memory devices offer performance that may not be entirely satisfactory in certain applications.
In particular, as is known, during the programming operation, an injection of electric charges occurs within the floating gate for effect of a phenomenon called “Fowler-Nordheim tunneling”; such technique provides for the formation of a strong electric field between the control gate and the drain terminal of the memory transistor, so that the electric charges are able to pass through the oxide layer and reach the floating gate buried therein.
During such programming operation, the source, drain and control terminals are biased in such a way that the memory transistor is turned off, i.e., it has no channel current from the drain terminal to the source terminal thereof; in fact, this would cause an unnecessary waste of electric power and a great difficulty to control the injection of electric charges within the floating gate.
However, the more and more increasing miniaturization of memory transistors in view of demands for high integration of the corresponding memory devices, involves that so-called “short-channel effects” (i.e., alterations of the electric properties of the transistors being caused by extremely small channel lengths) become more and more limiting.
A short-channel effect, known as “Drain-Induced Barrier Lowering” (DIBL), implies that, because of the voltage difference between the drain terminal and the source terminal of the memory transistor, a channel current may still generate during the programming operation, even in the absence of a command signal applied to its control terminal. For this reason, typically the source terminal of the memory transistor is biased, during the programming operation, at a voltage value high enough (and experimentally determined) to turn off the memory transistor for any voltage value at its drain terminal (technique known as source line pre-charge).
However, such solution is not fully satisfactory; in fact the biasing of the terminals of the memory transistor is performed through bias voltages that are typically generated and supplied by driver circuits implemented within the memory device; such driver circuits, not able to have an infinite bandwidth, provide the bias voltages in a finite time different from zero, according to a transient having a substantially ramp trend (instead of a step trend). Since each transient (of each bias voltage) has its own characteristic slope, it happens that, before the bias voltage at the source terminal of the memory transistor has reached a target value thereof (such as to inhibit its turning on), between the drain terminal and the source terminal of the memory transistor there is a voltage difference (corresponding to the slope difference of the transients of the respective bias voltages) such as to determine a channel current due to the above-mentioned DIBL effect. Such current, causing hot carrier injection within the oxide layer and the floating gate, determines an alteration of the threshold voltage of the memory transistor, which causes a substantial uncontrollability of the programming thereof; such phenomenon is cumulative, so that it is particularly harmful in applications that require a high number of programming and erasing operations (e.g., for memory cards for accessing pay television services, or “Pay-TV”).
Even using driver circuits, which can be expensive, having such high performance that make the transients of the bias voltages more rapid, it would be difficult to have a complete cancellation of the DIBL effect, or to have such significant reduction thereof to justify the considerable needed additional costs.